The present invention relates to a packet data communication apparatus for switching variable-length packets in data transmission of IP (Internet Protocol), for example, and fixed-length packets (generally called cells) in data transmission of ATM (Asynchronous Transfer Mode).
Nowadays, data traffic is increasing on networks, especially, on the Internet. There are moves toward executing high-quality and high-reliability services such as transaction processes which have been done on leased lines, on the Internet for the purpose of cost reduction. To cope with this tendency, there have been demands for larger capacity, higher speed and improved reliability of packet data communication apparatus as well as the transmission lines.
JP-A-11-154954 published on Jun. 8, 1999 (corresponding to U.S. Ser. No. 08/193,414 and EP 0918419A; hereafter referred to as Literature 1) discloses a technology regarding for increasing the capacity of an ATM switch. This ATM switch has n pieces of cell distributors respectively connected input highways and n pieces of cell assemblers respectively connected to output highways, and k pieces of unit ATM switches arranged in parallel having each switching capacity of n×n. Each of the n cell distributors and each of the n assemblers are connected to k pieces of unit ATM switches. Each cell distributor includes n queue buffers corresponding to the n cell assemblers. When receiving a cell from the input highway, the cell is buffered in a queue buffer corresponding to the cell assembler to which the cell is to be output, in other words, into a queue buffer corresponding to the destination of the cell. The cell distributor reads cells successfully from a selected queue buffer up to a number specified by a readout count specifying register, and outputs in parallel k cells bound for the same destination to k unit ATM switches at almost the same timing. The reason why cells are output in parallel at almost the same timing is to preserve the order of cell sequence. A cell assembler receives k cells bound for the same destination from the k unit ATM switches. If cells queued in the selected buffer are fewer than the number specified by the readout count specifying register, dummy cells are generated as many as a number of that difference, and the cells buffered in the selected queue buffer and dummy cells are output in parallel to the k unit ATM switches at almost the same timing. The cell assembler discards the dummy cells on receiving dummy cells from the k unit ATM switches. The technology disclosed in literature 1, by using the configuration mentioned above, performs load balancing on cell basis and increases the capacity of the ATM switch.
Literature 1 states that the unit ATM switches are of a shared buffer type, an output buffer type, or a crosspoint buffer type, none of which suffer from internal blocking of data traffic. The structure of the shared buffer type switch is shown in FIG. 25. Cells input from inputs 500 are multiplexed in time division by a cell multiplexer 501. Then, the time-division-multiplexed cells are stored in a shared buffer memory 503. More specifically, based on header information, cells are controlled by a controller 502 so that they are stored in queue buffers allotted for respective output lines logically configured in the shared buffer memory 503. The cells, which are read from the shared buffer memory at specified timing allotted to respective output lines 505, are demultiplexed by a cell demultiplexer 504 and output to respective output lines. The structure of the output buffer type switch is shown in FIG. 26. The cells input from the input lines 500 are time-division-multiplexed by the cell multiplexer 501 and output to a shared bus 506. Before being sent on respective output lines 505, cells on the shared bus are filtered by each address filter (AF) 507 in such a way that cells having the same destination address as specified in the address filter 507 and only cells related to the same route are filtered and stored in the queue buffers 508. From the queue buffers 508, cells are read at speed of the output lines 505. The structure of the crosspoint type switch is shown in FIG. 27. Cells input from the input lines 500 are stored in queue buffers 509 provided at their intersections with the output lines 505. Each output line 505 conducts arbitration among the corrected queue buffers 509 which are connected to the same output line 505. All of the shared buffer type, output buffer type and crosspoint buffer type switches have a buffering means to absorb collisions of cell output.
A technology that uses crossbar switches is disclosed in “Tiny Tera: Packet Switch Core &#34” by Nick McKeown, Martin Izzard, Adisak Mekkitikul, William Ellersack, and Mark Horowitz, IEEE MICRO, January/February 1997 (hereafter referred to as literature 2). The switch disclosed in literature 2 seems to be a switch for the most part as illustrated in FIG. 28. In the preceding stage of a crossbar switch 706 with n input ports and n output ports, there are provided n port cards 701, and an input buffer 703 is provided for each port card 701. Variable length packets input through input lines 700 are divided into fixed length packets (cells). The cells stored in each input buffer 703 are subjected to connection scheduling between the input and output ports of the switch 706, and then output from the port card 701, and switched by the crossbar switch 706. The connections between the input and output ports are changed once for every cell. In this configuration, each input buffer 703 is divided into n queue buffers (VOQ Virtual Output Queue) corresponding to different output ports, and it is made possible to read any queue buffer specified by the scheduler 705, thereby preventing a decrease in throughput due to HOL (Head Of Line) Blocking. The crossbar switch 706 slices a cell 704 into pieces of 64-bit data, for example, which are processed in parallel by a plural switch planes.
JP-A-2000-232482 published on Aug. 22, 2000 (which corresponds to U.S. Ser. No. 09/362,134 and EP1009 132A; hereafter referred to as literature 3) discloses a packet switch using crossbar switches. In this packet switch, at the input-side interface of the switch, a plurality of variable length packets are loaded in fixed length containers regardless of where packets are divided, and switching is performed by the unit of container. In this switching, large processing unit of containers enables parallel expansion of switching and thereby realizes a large capacity switching apparatus.
JP-A-5-191440 published on Jul. 30, 1993 (which corresponds to U.S. Pat. No. 5,414,696; hereafter referred to as literature 4) discloses a cell switch including a cell switch that operates as a working system, a cell switch that operates as a protection system, and a selector for switching over the working system and the stand-by system. Identical cells are input to the two cell switches at the same phase. However, the cells output from the two cell switches sometimes differ in the timing. Therefore, the selector performs switch-over from one system to another at the timing when idle cells are detected at the output of both switches.
The packet switch disclosed in literature 1 is superior in expandability. However, the unit switches arranged in parallel are having a buffering element to prevent output collisions. Therefore, when expansion switch planes are added without stopping the operation of the ATM switch, there is a possibility that the order of cells is reversed due to discrepancy in buffering state among switch planes. Thus, it is difficult to expand or decrease the switch capacity or maintain the switch apparatus without interrupting communication service. Furthermore, literature 1 does not disclose a redundancy of switch configuration.
In the switch of literature 2, crossbar switches are used, and because this switch system has distributed buffers and bufferless crossbar, in which the access speed of buffer memories is less likely to be a bottleneck. Therefore, crossbar switch is more suitable for capacity expansion compared with the shared resource type, such as the shared buffer type. However, when constructing an ultra-large capacity switch to support high-speed transmission lines in near future, in crossbar switches that use ATM cells or cells obtained by dividing variable length packets (cells are hereafter referred to data of short fixed lengths of about 64 bytes) as processing units will have a bottleneck of scheduling time that decides connection relationship of input and output ports cell by cell. Therefore, it will become difficult to configure a crossbar switch with high throughput. Moreover, literature 2 does not disclose how to expand or decrease the switch capacity, or perform maintenance of the switch nor does it disclose a redundancy of switch configuration.
Literature 3 does not disclose that the switch is formed by crossbar switches. Nor does literature 3 disclose how to expand or decrease the switch capacity and how to maintain the switch, nor does it disclose a switch redundancy configuration.
For the switch with a redundancy configuration as shown in literature 4, twice as much as the amount of hardware is required for the switch. Therefore, it is difficult to configure a packet communication apparatus in a compact size and at low cost. Moreover, literature 4 does not disclose how to expand or decrease the switch capacity, or how to perform maintenance of the switch apparatus without interrupting communication service.